By Himanshu Bhatnagar
Advanced ASIC Chip Synthesis: utilizing Synopsys® Design Compiler® actual Compiler® and PrimeTime®, Second Edition describes the complex strategies and methods used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. additionally, the complete ASIC layout move method distinctive for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this booklet is on real-time software of Synopsys instruments, used to wrestle a number of difficulties obvious at VDSM geometries. Readers might be uncovered to a good layout method for dealing with advanced, sub-micron ASIC designs. value is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to structure, actual synthesis, and static timing research. At each one step, difficulties comparable to every section of the layout circulation are pointed out, with options and work-around defined intimately. moreover, the most important concerns similar to format, together with clock tree synthesis and back-end integration (links to structure) also are mentioned at size. in addition, the ebook comprises in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding kinds, certain in the direction of optimum synthesis answer.
goal audiences for this booklet are practising ASIC layout engineers and masters point scholars venture complex VLSI classes on ASIC chip layout and DFT strategies.
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Extra resources for Advanced ASIC Chip Synthesis Using Synopsys Tools
Let us just presume that the design has been fully routed with minimal congestion and area. The finished layout surface must then be extracted to get the actual parasitic capacitances and interconnect RC delays. Depending upon the layout tool and the type of extraction, the extracted values are generally written out in the SDF format for the interconnect RC delays, while the parasitic information is generated as a string of set_load commands for each net in the design. In addition, if a hierarchical place and route has been performed, the physical placement location of cells in the PDEF format should also be generated.
JTAG or boundary scan is primarily used for testing the board connections, without unplugging the chip from the board. The JTAG controller and surrounding logic may also be generated directly by DC. 4 Formal Verification The concept of formal verification is fairly new to the ASIC design community. Formal verification techniques perform validation of a design using mathematical methods without the need for technological considerations, such as timing and physical effects. They check for logical functions of a design by comparing it against the reference design.
Also, the clock transition is specified because of the high fanout associated with the clock TUTORIAL 29 network. The high fanout suggests that the clock network is driving many flip-flops, each having a certain amount of pin capacitance. This gives rise to slow input ramp time for the clock. The fixed transition value (again approximating the final clock tree number) of clock prevents PT from calculating incorrect delay values, that are based upon the slow input ramp to the flops. The script to perform the hold-time analysis at the pre-layout level is shown below.
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